Semiconductor memory apparatus, and divisional program control circuit and program method therefor

ABSTRACT

A semiconductor memory apparatus includes a program pulse generation block configured to generate write control signals and a program completion signal; a divisional program control circuit configured to generate a divisional programming enable signal according to a predetermined number of program division times, in response to the program completion signal; and a controller configured to generate the programming enable signal in response to the divisional programming enable signal.

CROSS-REFERENCES TO RELATED APPLICATION

The present application claims priority under 35 U.S.C. §119(a) toKorean application number 10-2011-0114429, filed on Nov. 4, 2011, in theKorean Intellectual Property Office, which is incorporated herein byreference in its entirety.

BACKGROUND

1. Technical Field

The present invention relates to a semiconductor system, and moreparticularly, to a semiconductor memory apparatus, and a divisionalprogram control circuit and a program method therefor.

2. Related Art

A PCRAM (phase change RAM) is a memory apparatus which uses a phasechange characteristic of a specified substance constituting a memorycell. A phase change substance may be converted into an amorphous stateor a crystalline state depending upon a temperature condition, and mayinclude, for example, a chalcogenide-based alloy. A representative phasechange substance includes a Ge2Sb2Te5 (hereafter referred to as a ‘GST’)substance which comprises germanium, antimony and tellurium.

Most substances have different melting points and crystallizationtemperatures, and their degree of crystallization may vary dependingupon a cooling time and a cooling temperature. This may serve as aunique characteristic of a substance. In particular, a GST substance maybe more clearly distinguished between the amorphous state and thecrystalline state than other substances.

FIG. 1 is a graph for explaining phase changes of a general phase changesubstance depending upon a temperature. A GST substance will be used asan example.

When GST is applied with a high temperature equal to or greater than themelting point of GST for a predetermined time (several tens to severalhundreds nanoseconds [ns]) and is quenched for a preset time Tq, theamorphous state of the GST is maintained as it is, and a resistancevalue becomes several hundreds kilohms (kΩ) to several megohms (MΩ).

Also, if the GST is maintained at a crystallization temperature for apreselected time (several hundreds ns to several microseconds [μs]) andis then cooled, the GST is converted into the crystalline state and theresistance value becomes several kΩ to several tens kΩ. As a time formaintaining the crystallization temperature is lengthened, thecrystalline state improves and, accordingly the GST has a smallerresistance value.

FIG. 2 is another graph for explaining phase changes of the generalphase change substance depending upon a temperature. Similarly, the GSTsubstance will be used as an example.

FIG. 2 shows an example in which the GST is crystallized by applying atemperature near the melting point of GST for a predetermined time, andslowly cooling the GST. Even in this case, the resistance value of theGST becomes several kΩ to several tens kΩ, and as a cooling time islengthened, the crystalline state improves. Also, a crystallization timeis shortened when compared to FIG. 1.

In order to use such a characteristic of the GST, heat may be directlyapplied to the GST; or Joule's heat may be electrically generated bycurrent flow through a conductor or a semiconductor to convert the GSTbetween the amorphous state and the crystalline state.

While FIGS. 1 and 2 show general operations of the phase change memoryapparatus, the method of FIG. 2 is mainly used since a set data programtime, that is, a time required for crystallizing the GST is short.

FIG. 3 is a configuration diagram of a cell array of a conventionalphase change memory apparatus.

Referring to FIG. 3, each memory cell MC is constituted by a phasechange substance GST and a switching element which are connected betweena word line WL and a bit line BL.

Program operations of a phase change memory apparatus will be describedbelow with reference to FIG. 4.

FIG. 4 is a configuration diagram of a conventional phase change memoryapparatus.

Referring to FIG. 4, a phase change memory apparatus 1 includes aprogram pulse generation block 11, a write driver 12, and a memory block13.

The program pulse generation block 11 is configured to generate a firstwrite control signal RESETEN and second write control signals SETP<0:n>in response to a programming enable signal PGMP. The program pulsegeneration block 11 provides the first write control signal RESETEN andthe second write control signals SETP<0:n> to the write driver 12.Further, when the operation of generating the first write control signalRESETEN and the second write control signals SETP<0:n> is completed, theprogram pulse generation block 11 generates a program completion signalPGMNDP and transmits the program completion signal PGMNDP to acontroller.

The write driver 12 is configured to be driven in response to a writeenable signal WDEN. The write driver 12 is provided with the first writecontrol signal RESETEN and the second write control signals SETP<0:n>,and provides program current I_PGM to the memory block 13 in response todata DATA to be programmed and bit line select switch control signalsYSW<0:m>.

Accordingly, in the memory block 13, as the resistant state of a GST ischanged depending upon the level of the data DATA to be programmed, thedata DATA can be recorded.

FIG. 5 is an example block diagram of the program pulse generation blockshown in FIG. 4.

Referring to FIG. 5, the program pulse generation block 11 is configuredto include an initial pulse generation unit 111, a reset pulsegeneration unit 113, and a quenching pulse generation unit 115.

The initial pulse generation unit 111 is configured to generate a periodsetting signal QSSETP in response to the programming enable signal PGMPwhich is provided from the controller. The period setting signal QSSETPis a signal which determines a time to supply heat near a melting pointto the GST. The initial pulse generation unit 111 enables the periodsetting signal QSSETP after counting a preset time in response to theprogramming enable signal PGMP.

The reset pulse generation unit 113 is configured to generate the firstwrite control signal RESETEN in response to the programming enablesignal PGMP and a reset signal IRSTP which is generated by delaying theperiod setting signal QSSETP by a predefined time.

The quenching pulse generation unit 115 is configured to generate thesecond write control signals SETP<0:n> which have different enableperiods, in response to the programming enable signal PGMP and theperiod setting signal QSSETP. Further, the quenching pulse generationunit 115 generates a program completion signal PGMNDP when thegeneration of the second write control signals SETP<0:n> is completed.

According to such a configuration, the reset pulse generation unit 113generates the first write control signal RESETEN during a period fromafter the programming enable signal PGMP is enabled to when the resetsignal IRSTP is enabled. The quenching pulse generation unit 115 enablesthe second write control signals SETP<0:n> at the same levels until theperiod setting signal QSSETP is enabled, and generates the second writecontrol signals SETP<0:n>, after the period setting signal QSSETP isgenerated.

FIG. 6 is a timing diagram illustrating program operations of theconventional phase change memory apparatus.

As a program command PGM is applied, the programming enable signal PGMPis generated from the controller. Accordingly, the initial pulsegeneration unit 111 operates and generates an internal clock enablesignal IPWEN. Then, after an internal clock ICK is generated, countingcodes Q<0:3> are generated by counting the preset time, and when thecounting is completed, the period setting signal QSSETP is generated.

The reset pulse generation unit 113 enables the first write controlsignal RESETEN in response to the programming enable signal PGMP, anddisables the first write control signal RESETEN as the reset signalIRSTP is enabled. The reset signal IRSTP is generated by delaying theperiod setting signal QSSETP by the predefined time. During a period inwhich the first write control signal RESETEN is enabled, programmingcurrent is generated from the write driver 12 and is provided to a bitline BL0.

The quenching pulse generation unit 115 generates a count enable signalCKEN (CNTENB) and an internal clock QSCK in response to the periodsetting signal QSSETP. Accordingly, the second write control signalsSETP<0:3> which have different enable periods are generated. Whengeneration of the second write control signal SETP<0:3> is completed, aquenching pulse completion signal QSND is disabled, and then, when areset signal QSRSTP is enabled, the program completion signal PGMNDP isoutputted. In this case, the current driving force of the write driver12 is sequentially damped according to the enable periods of the secondwrite control signals SETP<0:3>, and a quenching pulse is provided tothe GST.

In a program operation, a word line maintains a high potential (equal toor greater than VCC) when a word line select switch is in a disabledstate, and is discharged to the level of a ground voltage as the wordline select switch is enabled. A current path is formed via a bit linethat is selected by the write driver 12. The current path is formed bythe write driver 12 through a bit line select switch, the bit line, aswitching element and the GST to the word line.

When the current path is formed in this way, the amount of currentdriven by the write driver 12 is determined according to the first writecontrol signal RESETEN or the second write control signals SETP<0:n>depending upon a data level (0/1) to be programmed, and the programcurrent is provided to the memory cell through the bit line. Forexample, when assuming that an amount of current provided by the firstwrite control signal RESETEN is 100%, an amount of current provided tothe memory cell when all of the second write control signals SETP<0:3>are enabled is controlled to a rate of 30 to 90%.

In the program operation, the current provided through the bit line isprovided in a rectangular type in the case of reset data. In the case ofset data, the current is provided initially in a type similar to arectangular type but is then provided by being reduced into a step typeby the second write control signals SETP<0:n>. Further, current consumedin a program operation is about 1 mA. Thus, 16 mA is consumed whenprogramming is performed by the unit of X16, and 32 mA is consumed whenprogramming is performed by the unit of X32.

In this regard, since a bit line select switch is connected to eachcell, there is no problem with how current is supplied. However, since aplurality of cells are connected to a word line select switch, one wordline select switch should take charge of current supply for all the ofplurality of cells, and the size of a transistor constituting the wordline select switch should be correspondingly increased.

An increase in the size of a transistor leads to an increase in the sizeof a chip. Also, when a large amount of current flows through thetransistor at one time, a program error may be caused due to aninfluence of noise resulting from ground bounce.

SUMMARY OF THE INVENTION

In one embodiment of the present invention, a semiconductor memoryapparatus includes: a program pulse generation block configured togenerate write control signals and a program completion signal inresponse to a programming enable signal; a divisional program controlcircuit configured to generate a divisional programming enable signalaccording to a predetermined number of program division times, inresponse to the program completion signal; and a controller configuredto generate the programming enable signal in response to the divisionalprogramming enable signal.

In another embodiment of the present invention, a semiconductor memoryapparatus includes: a program pulse generation block configured tooutput write control signals in response to a programming enable signalwhich is generated according to a divisional programming enable signal;and a write driver configured to provide a program pulse generated inresponse to the write control signals, to a memory block.

In another embodiment of the present invention, a divisional programcontrol circuit is connected with a program pulse generation block whichgenerates a program completion signal, in response to a programmingenable signal which is generated according to a divisional programmingenable signal, and the divisional program control circuit generates thedivisional programming enable signal according to a predetermined numberof program division times, in response to the program completion signal.

In another embodiment of the present invention, a program method for asemiconductor memory apparatus includes: inputting program data to thesemiconductor memory apparatus comprising a program pulse generationblock; repeatedly generating a programming enable signal with a presetcycle in correspondence to a predetermined number of program divisiontimes by the program pulse generation block; and programming data to aselected region of a memory block by a write driver, in response to theprogramming enable signal.

BRIEF DESCRIPTION OF THE DRAWINGS

Features, aspects, and embodiments are described in conjunction with theattached drawings, in which:

FIG. 1 is a graph for explaining phase changes of a general phase changesubstance depending upon a temperature;

FIG. 2 is another graph for explaining phase changes of the generalphase change substance depending upon a temperature;

FIG. 3 is a configuration diagram of a cell array of a conventionalphase change memory apparatus;

FIG. 4 is a configuration diagram of a conventional phase change memoryapparatus;

FIG. 5 is a block diagram exemplifying the program pulse generationblock shown in FIG. 4;

FIG. 6 is a timing diagram illustrating program operations of theconventional phase change memory apparatus;

FIG. 7 is a configuration diagram of a semiconductor memory apparatus inaccordance with an embodiment of the present invention;

FIG. 8 is a configuration diagram of a divisional program controlcircuit in accordance with an embodiment of the present invention;

FIG. 9 is a view exemplifying the divisional program control circuitshown in FIG. 8;

FIG. 10 is a view exemplifying the mode determination unit shown in FIG.8;

FIG. 11 is a view exemplifying a pulse outputting section shown in FIG.9;

FIG. 12 is a view exemplifying the divisional code generating sectionshown in FIG. 9;

FIG. 13 is a view exemplifying a program pulse generation block whichmay be applied to an embodiment the present invention;

FIG. 14 is an exemplary view illustrating a configuration of the firstcounting section shown in FIG. 13;

FIG. 15 is a view exemplifying a comparing section shown in FIG. 13;

FIG. 16 is a view illustrating configurations of a count unit shown inFIG. 9 and a second counting section shown in FIG. 13;

FIG. 17 is a view exemplifying a write driver which may be applied to anembodiment of the present invention;

FIG. 18 is a timing diagram illustrating operations of a semiconductormemory apparatus according to a divisional program mode; and

FIG. 19 is a timing diagram illustrating program operations when thenumber of division times is 4.

DETAILED DESCRIPTION

Hereinafter, a semiconductor memory apparatus, and a divisional programcontrol circuit and a program method therefor according to the presentinvention will be described below with reference to the accompanyingdrawings through example embodiments.

FIG. 7 is a configuration diagram of a semiconductor memory apparatus inaccordance with an embodiment of the present invention.

Referring to FIG. 7, a semiconductor memory apparatus 10 may include aprogram pulse generation block 100, a divisional program control circuit200, a controller 300, a write driver 400 and a memory block 500. Theprogram pulse generation block 100 may be configured to generate a firstwrite control signal RESETEN and second write control signals SETP<0:n>in response to a programming enable signal PGMP. The divisional programcontrol circuit 200 may be configured to generate a divisionalprogramming enable signal DIVPGMP and division codes DIVPGM<0:x>according to a preset division mode. The divisional program circuit 200may be connected with the program pulse generation block 100. Thecontroller 300 may be configured to provide program operation-relatedcontrol signals including the programming enable signal PGMP, an addressand a data signal. The write driver 400 may be configured to generateprogram current I_PGM for programming input data DATA in response to thewrite control signals RESETEN and SETP<0:n> provided from the programpulse generation block 100 and bit line select switch control signalsYSW<0:m>. The memory block 500 may include a plurality of memory cellsand may be configured to record data in respective memory cellsaccording to current provided from the write driver 400.

In the semiconductor memory apparatus 10, the divisional program controlcircuit 200 generates the divisional programming enable signal DIVPGMPfor allowing a program operation to be repeatedly performed according tothe preset division mode, that is, by the number of divided regions of amemory block, and provides the divisional programming enable signalDIVPGMP to the controller 300. The controller 300 provides theprogramming enable signal PGMP generated in response to the divisionalprogramming enable signal DIVPGMP, to the program pulse generation block100 so that a program operation is performed a predetermined number oftimes (iterations). Thus, the program pulse generation block 100 maygenerate the programming enable signal PGMP with a preset cycle incorrespondence to a predetermined number of program division times,where the programming enable signal PGMP is repeatedly generated with agenerating cycle of the program completion signal.

In addition, the divisional program control circuit 200 also generatesthe division codes DIVPGM<0:x> and provides the division codesDIVPGM<0:x> to the controller 300. The controller 300 drives a writedriver 400 which is designated by the division codes DIVPGM<0:x> so thata program operation is performed in a corresponding region of a memoryblock.

Operations of the respective component parts will be described below indetail.

The program pulse generation block 100 generates the first write controlsignal RESETEN and the second write control signals SETP<0:n> inresponse to the programming enable signal PGMP generated by thecontroller 300. The program pulse generation block 100 provides thefirst write control signal RESETEN and the second write control signalsSETP<0:n> to the write driver 400. Further, when the operation ofgenerating the first write control signal RESETEN and the second writecontrol signals SETP<0:n> is completed, the program pulse generationblock 100 generates a program completion signal PGMNDP and transfers theprogram completion signal PGMNDP to the divisional program controlcircuit 200. That is to say, when a program operation is completed onetime by the first and second write control signals RESETEN and SETP<0:n>generated by the program pulse generation block 100, the programcompletion signal PGMNDP is communicated to the divisional programcontrol circuit 200 as an indication that a program operation hascompleted, so that a subsequent program operation may be performedaccording to the division mode.

The write driver 400 is driven in response to a write enable signalWDEN. The write driver 400 is provided with the first write controlsignal RESETEN and the second write control signals SETP<0:n>, and thewrite driver 400 provides the program current I_PGM to the memory block500 in response to the data DATA to be programmed and the bit lineselect switch control signals YSW<0:m>.

According to this fact, data may be recorded in the memory block 500according to the level of the data DATA to be programmed. In anembodiment of the present invention, the memory block 500 may beconfigured using memory cells in and from which data are recorded andsensed by a current driving scheme. The memory cells in and from whichdata are recorded and sensed by the current driving scheme include, forexample, phase change memory cells, and magnetic memory cells.

The divisional program control circuit 200 uses the program completionsignal PGMNDP provided from the program pulse generation block 100, as aclock signal, and generates the divisional programming enable signalDIVPGMP and the division codes DIVPGM<0:x> according to the presetdivision mode. In other words, the divisional program control circuit200 performs a counting operation according to a predetermined number ofdivisional program times, and transfers the divisional programmingenable signal DIVPGMP generated as a result of the counting operation,to the write driver 400 and the controller 300. Further, the divisionalprogram control circuit 200 generates the division codes DIVPGM<0:x> fordetermining divisional program regions according to the preset divisionmodes. The divisional program regions may be set, but not limited to,using a fuse option, a mode register set (MRS) or a test mode signal.

In an embodiment of the present invention, the divisional programcontrol circuit 200 may be configured, without a limiting sense, tooperate after a program operation is completed one time by the writecontrol signals RESETEN and SETP<0:n> which are generated by the programpulse generation block 100.

If the division mode is 1, that is, a region to be programmed is notdivided, a program mode is ended after the program is performed one timeaccording to the first and second write control signals RESETEN andSETP<0:n>.

Meanwhile, when a program region is divided into two (the division modeis 2), program is repeated two times, and when a program region isdivided into four (the division mode is 4), program is repeated fourtimes. In this way, program is repeated by a number by which the programregion is divided.

When a program operation is performed all at once without dividing theprogram region, an amount of current, with which a word line selectswitch should be charged, increases as a program handling unitincreases. Accordingly, the size of the word line select switchincreases, and as peak current flows, a program error may be caused dueto an influence of noise resulting from ground bounce.

However, in an embodiment of the present invention, as the programregion is divided, peak current may be reduced and control may be madeso that an error does not occur.

Meanwhile, although the divisional program control circuit 200 is shownindependently of the program pulse generation block 100 in FIG. 7, thedivisional program control circuit 200 may be configured to be includedin the program pulse generation block 100. That is to say, the programpulse generation block 100 may include the divisional program controlcircuit 200.

FIG. 8 is a configuration diagram of a divisional program controlcircuit in accordance with an embodiment of the present invention, andFIG. 9 is a view exemplifying the divisional program control circuitshown in FIG. 8.

Referring to FIGS. 8 and 9, the divisional program control circuit 200may be configured to include a count unit 210, a mode determination unit220, a divisional program pulse generation unit 230, and a region selectcontrol unit 240.

The count unit 210 is configured to count the number of divisionalprogram times in response to a clock signal DIVCNTCK, a set signalDIVSETP and a reset signal RSTP which are generated from a count enablesignal DIVCNTB and the program completion signal PGMNDP. As the clocksignal DIVCNTCK generated from the program completion signal PGMNDP isused, the counting operation for divisional program may be performedafter a program operation is completed one time. The count unit 210outputs count signals DIVCNT<0:y> and count completion signalsBCNTB<0:y> as a result of such a counting operation. The count signalsDIVCNT<0:y> are transferred to the region select control unit 240 whichwill be described later in detail, and the count completion signalsBCNTB<0:y> are transferred to the mode determination unit 220.

As shown in FIG. 9, the count unit 210 may be configured, for example,using three stage down counters (DNCNT) 211, 213 and 215.

The first stage down counter 211 performs counting in response to theclock signal DIVCNTCK when a count enable signal DIVCNTB is enabled, forexample, to a low level, and outputs the first count signal DIVCNT<0>and the first count completion signal BCNTB<0>.

The first count completion signal BCNTB<0> is used as a signal forenabling the next stage down counter 213. Accordingly, the down counter213 outputs the second count signal DIVCNT<1> and the second countcompletion signal BCNTB<1>, and the down counter 215 outputs the thirdcount signal DIVCNT<2> and the third count completion signal BCNTB<2>.

The count completion signals BCNTB<0:2> outputted from the respectivedown counters 211, 313 and 215 may be provided to the mode determinationunit 220, and the count signals DIVCNT<0:y> may be provided to thedivisional code generating section 241 of the region select control unit240. Thus, the count unit 210 may comprise a plurality of counters thatare connected in series to count a number of divisional program times(iterations) in response to a count enable signal.

Due to this fact, the count unit 210 operates in such a manner that anext program pulse may be generated after a program operation iscompleted as one program pulse is generated. If all divisionalprogramming is completed, the count unit 210 is reset by the resetsignal RSTP so the operation of the count unit 210 is ended.

The mode determination unit 220 is configured to generate a modedetermination signal BCNTINB in response to the count enable signalDIVCNTB, the count completion signals BCNTB<0:y> and division modesignals DIVMOD<0:y>. Namely, if counting is completed in the count unit210, the mode determination unit 220 generates the mode determinationsignal BCNTINB which determines the number of times that the divisionalprogram is performed, according to the preset division mode signalsDIVMOD<0:y>.

The mode determination signal BCNTINB generated by the modedetermination unit 220 is provided to the divisional program pulsegeneration unit 230. As shown in FIG. 9, the divisional program pulsegeneration unit 230 may be configured to include a period settingsection 231 and a pulse outputting section 233.

The period setting section 231 is configured to generate a divisionalperiod enable signal IDIVPGM which indicates that it is a divisionalprogram period. The period setting section 231 may generate thedivisional period enable signal IDIVPGM in response to the modedetermination signal BCNTINB, the clock signal DIVCNTCK, the set signalDIVSETP and the reset signal RSTP. In detail, when the divisional periodenable signal IDIVPGM is set to a high level according to the set signalDIVSETP, the divisional period enable signal IDIVPGM is reset to a lowlevel when the clock signal DIVCNTCK is inputted, and indicates that itis a divisional program period.

The pulse outputting section 233 is configured to generate thedivisional programming enable signal DIVPGMP in response to theprogramming enable signal PGMP, the divisional period enable signalIDIVPGM and the program completion signal PGMNDP, and the pulseoutputting section 233 provides the divisional programming enable signalDIVPGMP to the controller 300. The pulse outputting section 233 isconfigured to transfer the programming enable signal PGMP (notifyingstart of a program operation) without modifying the programming enablesignal PGMP before the divisional period enable signal IDIVPGM is set tothe high level, and the pulse outputting section 233 is configured totransfer the program completion signal PGMNDP when the divisional periodenable signal IDIVPGM is enabled to the high level.

In an embodiment of the present invention, the period setting section231 may be constituted by, but not limited to, a down counter.

The region select control unit 240 may be configured to include thedivisional code generating section 241 as shown in FIG. 9. Thedivisional code generating section 241 is configured to generate thedivision codes DIVPGM<0:x> in response to the divisional period enablesignal IDIVPGM, the count signals DIVCNT<0:y> and the division modesignals DIVMOD<0:y>. The division mode signals DIVMOD<0:y> may be set,but not limited to, using a fuse option, a mode register set (MRS) or atest mode signal.

The divisional code generating section 241 may combine some of thedivision mode signals DIVMOD<0:y>, for example, the division modesignals DIVMOD<0:3>, and the count signals DIVCNT<0:2> and generate thedivision codes DIVPGM<0:7> as flag signals, and the divisional codegenerating section 241 may transfer the division codes DIVPGM<0:7> tothe controller 300.

In an embodiment of the present invention, the division mode signalsDIVMOD<0:3> may be generated from division option codes DIVMODE<0:1>which are preset to a fuse option, an MRS or a test mode signal.

As is apparent from the above descriptions, the divisional programcontrol circuit 200 in accordance with an embodiment of the presentinvention performs program operations by dividing a program region of amemory block so that peak current is reduced and memory cells are stablyprogrammed.

To this end, the count unit 210 performs counting until the reset signalRSTP is enabled according to the program completion signal PGMNDP. Whencounting by the count unit 210 is completed, the mode determination unit220 determines the division mode according to the preset division modesignals DIVMOD<0:y> in correspondence to divided regions and generatesthe mode determination signal BCNTINB. Also, if the period settingsection 231 generates the divisional period enable signal IDIVPGM whichindicates that it is a divisional program period, the pulse outputtingsection 233 generates the divisional programming enable signal DIVPGMPaccording to a level of the divisional period enable signal IDIVPGM, andthe region select control unit 240 generates the division codesDIVPGM<0:x> which designate memory regions where divisional programmingis to be performed.

As a result, a specific write driver is driven by the division codesDIVPGM<0:x>, and as the program pulse generation block 100 generates thefirst write control signal RESETEN and the second write control signalsSETP<0:n>, the divisional program operation is performed a predeterminednumber of division times. Accordingly, as the first write control signalRESETEN and the second write control signals SETP<0:n> are generated thepredetermined number of division times, data may be selectivelyprogrammed to the memory cells.

FIG. 10 is a view exemplifying the mode determination unit shown in FIG.8.

Referring to FIG. 10, the mode determination unit 220 combines the countenable signal DIVCNTB, the count completion signals BCNTB<0:2> and thedivision mode signals DIVMOD<0:y>, and generates the mode determinationsignal BCNTINB.

In detail, the mode determination unit 220 selects and outputs the countenable signal DIVCNTB in a program mode with the number of divisiontimes of 1, selects and outputs only the first count completion signalBCNTB<0> in a program mode with the number of division times of 2,selects and outputs the first and second count completion signalsBCNTB<0> and BCNTB<1> in a program mode with the number of divisiontimes of 4, and selects and outputs all the first to third countcompletion signals BCNTB<0>, BCNTB<1> and BCNTB<2> in a program modewith the number of division times of 8.

To this end, control may be made such that the count unit 210 does notoperate when the number of division times is 1, only the first downcounter 211 of the count unit 210 is operated when the number ofdivision times is 2, the first and second down counters 211 and 213 ofthe count unit 210 are operated when the number of division times is 4,and the first to third down counters 211, 213 and 215 of the count unit210 are operated when the number of division times is 8.

Furthermore, it can be seen that a circuit configuration is simplifiedbecause the division mode signals DIVMOD<0:y> are configured to below-enabled so that the output of a down counter corresponding to aselected division mode is not selected but the output of an unselecteddown counter is selected.

FIG. 11 is a view exemplifying the pulse outputting section shown inFIG. 9.

When a program operation is initially started, the programming enablesignal PGMP is transferred unmodified as the divisional programmingenable signal DIVPGMP. In a period in which the divisional period enablesignal IDIVPGM indicating a divisional program period is generated,since the programming enable signal PGMP is disabled, the programcompletion signal PGMNDP is transferred as the divisional programmingenable signal DIVPGMP, by which a pulse signal DIVPGMP for divisionalprogram is generated.

FIG. 12 is a view exemplifying the divisional code generating sectionshown in FIG. 9.

The divisional code generating section 241 may comprise a decoder whichgenerates the division codes DIVPGM<0:7> in response to the divisionalperiod enable signal IDIVPGM, the count signals DIVCNT<0:2> and thedivision mode signals DIVMOD<0:2>. Moreover, while it is exemplified inFIG. 12 that the division codes DIVPGM<0:7> of 8 bits are generated andthe number of division times is set to 8 in maximum, it is conceivablethat the number of division times may be further increased.

Referring to FIG. 12, in a program mode with the number of divisiontimes of 1, the division codes DIVPGM<0:7> are all enabled (for example,to high levels).

When the number of division times is 2, even-numbered division codes ofthe division codes DIVPGM<0:7> are enabled in a first divisional programmode, and odd-numbered division codes of the division codes DIVPGM<0:7>are enabled in a second divisional program mode.

When the number of division times is 4, the division codes DIVPGM<0, 4>are enabled in a first divisional program mode, the division codesDIVPGM<1, 5> are enabled in a second divisional program mode, thedivision codes DIVPGM<2, 6> are enabled in a third divisional programmode, and the division codes DIVPGM<3, 7> are enabled in a fourthdivisional program mode.

Similarly, when the number of division times is 8, the division codesDIVPGM<0:7> are enabled sequentially enabled and are transferred to awrite driver and a controller.

FIG. 13 is a view exemplifying a program pulse generation block whichmay be included in the present invention.

Referring to FIG. 13, the program pulse generation block 100 includes aninitial pulse generation unit 110, a reset pulse generation unit 120,and a quenching pulse generation unit 130.

The initial pulse generation unit 110 is configured to generate theperiod setting signal QSSETP in response to the programming enablesignal PGMP which is provided from the controller 300. The periodsetting signal QSSETP is a signal for determining a time for providingheat near a melting point to a GST. The initial pulse generation unit110 enables the period setting signal QSSETP after counting apredetermined time interval in response to the programming enable signalPGMP.

The reset pulse generation unit 120 is configured to generate the firstwrite control signal RESETEN in response to the programming enablesignal PGMP and the reset signal IRSTP which is generated by delayingthe period setting signal QSSETP by a predefined time interval.

The quenching pulse generation unit 130 is configured to generate thesecond write control signals SETP<0:n> which have different enableperiods, in response to the programming enable signal PGMP and theperiod setting signal QSSETP. When the generation of the second writecontrol signals SETP<0:n> is completed, the quenching pulse generationunit 130 generates the program completion signal PGMNDP.

According to the configuration as described above, the reset pulsegeneration unit 120 generates the first write control signal RESETENduring a period from after the programming enable signal PGMP is enabledto until the reset signal IRSTP is enabled. The quenching pulsegeneration unit 130 enables the second write control signals SETP<0:n>at the same levels from after the programming enable signal PGMP isenabled to until the period setting signal QSSETP is enabled, andgenerates the second write control signals SETP<0:n> which arecontrolled in the enable periods thereof, after the period settingsignal QSSETP is generated.

Detailed descriptions will be given below.

First, the initial pulse generation unit 110 includes an input latchingsection 1101, a clock generating section 1103, a first counting section1105, a comparing section 1107, and a delaying section 1109.

The input latching section 1101 is configured to output the internalclock enable signal IPWEN and a count reset signal IPWRST in response tothe programming enable signal PGMP and the reset signal IRSTP. That isto say, if the programming enable signal PGMP is enabled, for example,to a high level, the internal clock enable signal IPWEN is activated toa high level, and if the reset signal IRSTP is enabled to a high level,the count reset signal IPWRST is activated to a high level.

In detail, the input latching section 1101 may be configured such thatthe internal clock enable signal IPWEN is enabled to the high level andthe count reset signal IPWRST is enabled to a low level. The inputlatching section 1101 may be configured using an R-S latch constitutedby a NAND gate or a NOR gate, or a flip-flop.

The clock generating section 1103 is configured to generate an internalclock ICK in response to the internal clock enable signal IPWEN. Inother words, the clock generating section 1103 outputs the internalclock ICK which toggles while the internal clock enable signal IPWEN isactivated to the high level.

The first counting section 1105 is configured to output counting codesQ<0:3> which are counted according to control of the internal clockenable signal IPWEN, the count reset signal IPWRST and the internalclock ICK. Namely, the first counting section 1105 performs a countingoperation according to control of the internal clock ICK when theinternal clock enable signal IPWEN is activated to the high level. Ifthe count reset signal IPWRST is activated to the high level, thecounting codes Q<0:3> outputted from the first counting section 1105 areinitialized. In this way, as the counting codes Q<0:3> are generatedusing the first counting section 1105, a circuit size may besignificantly reduced. The first counting section 1105 may be configuredby up counters.

The comparing section 1107 is configured to activate and output theperiod setting signal QSSETP when the counting codes Q<0:3> reach apreset value. In detail, the comparing section 1107 is configured tocompare the counting codes Q<0:3> with time control codes IPWSET<0:3>applied, and the comparing section 1107 is configured to activate theperiod setting signal QSSETP when the counting codes Q<0:3> are the sameas the time control codes IPWSET<0:3>. That is to say, the activationtiming of the period setting signal QSSETP may be controlled bycontrolling the time control codes IPWSET<0:3>.

In an embodiment of the present invention, the generation timing of theperiod setting signal QSSETP may be delayed by simultaneously increasingthe number of counters constituting the first counting section 1105 andthe number of time control codes IPWSET. This means that a time requiredfor melting the GST constituting a memory cell may be changed.

The delaying section 1109 is configured to delay the period settingsignal QSSETP by the predetermined time interval and output the resetsignal IRSTP. The delay value of the delaying section 1109 is set tosatisfy a prescribed timing margin. The reset signal IRSTP generated bythe delaying section 1109 resets the input latching section 1101 anddisables the internal clock enable signal IPWEN, and enables the countreset signal IPWRST such that the clock generating section 1103 and thefirst counting section 1105 are disabled.

The reset pulse generation unit 120 is enabled by the programming enablesignal PGMP and is disabled by the period setting signal QSSETP. Inother words, the reset pulse generation unit 120 generates the firstwrite control signal RESETEN for the time set by the time control codesIPWSET<0:3>, and provides the first write control signal RESETEN to thewrite driver 400.

Next, the quenching pulse generation unit 130 may be configured toinclude an input latching section 1301, a clock generating section 1303,a second counting section 1305, a reset controlling section 1307, and adelaying section 1309.

The input latching section 1301 is configured to output the count enablesignal CNTENB and the internal clock enable signal QSEN in response tothe period setting signal QSSETP and the reset signal QSRSTP. The clockgenerating section 1303 is configured to generate an internal clock QSCKin response to an internal clock enable signal QSEN. Namely, the clockgenerating section 1303 outputs the internal clock QSCK which toggleswhile the internal clock enable signal QSEN is activated to a highlevel.

The second counting section 1305 is configured to output the secondwrite control signals SETP<0:3> in response to a count enable signalCNTENB, the internal clock QSCK, the programming enable signal PGMP anda reset signal QSRSTP. Accordingly, the update cycle of the second writecontrol signals SETP<0:3> is controlled in correspondence to thetoggling cycle of the internal clock QSCK.

In an embodiment of the present invention, the second counting section1305 may be configured to include down counters. In this case, thesecond counting section 1305 operates while a final output is changedfrom 0x1111b to 0x0000b. If the final output becomes 0x0000b, the outputsignal of the second write control signal SETP<3> drives the resetcontrolling section 1307.

The reset controlling section 1307 is configured to enable the resetsignal QSRSTP when the code value of the second write control signalsSETP<0:3> outputted from the second counting section 1305 reaches apredetermined value, that is, when the output signal of the second writecontrol signal SETP<3> transitions from a high level to a low level.

To this end, the reset controlling section 1307 may include a count endcontrol part and a pulse generation part. The count end control partgenerates a quenching pulse completion signal QSND as counting of thesecond counting section 1305 is completed, and the pulse generation partgenerates the reset signal QSRSTP in response to the quenching pulsecompletion signal QSND. For example, the quenching pulse completionsignal QSND outputted from the count end control part maintains a highlevel by the programming enable signal PGMP, and transitions to a lowlevel when the second write control signals SETP<3> becomes the lowlevel. The pulse generation part enables the reset signal QSRSTP by thequenching pulse completion signal QSND transitioned to the low level.

The delaying section 1309 is configured to delay the reset signal QSRSTPby a preselected time and generates the program completion signalPGMNDP. The program completion signal PGMNDP is transmitted to thecontroller 300 and notifies that the program is completed.

FIG. 14 is an exemplary view illustrating a configuration of the firstcounting section shown in FIG. 13.

In an embodiment of the present invention, the first counting section1105 may be configured using a plurality of 1-bit up counters, and FIG.14 shows an example of an up counter.

Referring to FIG. 14, a 1-bit up counter 150 may include a signal inputpart 151, a latch part 153, and a carry generation part 155.

The signal input part 151 is configured to determine the level of thesignal of an input node A of the latch part 153 in response to a countenable signal, that is, the internal clock enable signal IPWEN and thefirst counting code Q<0> in an embodiment of the present invention.

The latch part 153 is configured to latch the signal outputted from thesignal input part 151 according to the control of the internal clock ICKand output the first counting code Q<0>. The carry generation part 155is configured to output a carry signal COUT according to the internalclock enable signal IPWEN and the first counting code Q<0>. The carrysignal COUT is used as a count enable signal of a next stage 1-bit upcounter. The internal node of the latch part 153 is initialized or ischanged to a specified level in response to the count reset signalIPWRST.

In detail, the signal input part 151 selects the resultant value of anoutput node Q when the internal clock enable signal IPWEN is disabled toa low level, and oppositely selects the resultant value of the outputnode Q and transfers the oppositely selected resultant value to the nextstage 1-bit up counter when the internal clock enable signal IPWEN isenabled to the high level.

The latch part 153 transfers the signal of the node A to a node C whenthe signal of the node A is a low level, and transfers the signal of thenode A to the output node Q when the signal of the node A is a highlevel.

If the count reset signal IPWRST becomes the high level, the output nodeQ is reset to a low level, and the carry generation part 155 operatesaccording to the signal applied to the output node Q of a previous stage1-bit up counter, which serves as a count enable signal. That is to say,according to the signal level of the signal applied to the output node Qof a previous stage 1-bit up counter, a next stage 1-bit up countertoggles.

FIG. 15 is a view exemplifying the comparing section shown in FIG. 13.

Referring to FIG. 15, the comparing section 1107 may include a pluralityof comparison parts 71, 72, 73 and 74 and a signal combination part 75.The plurality of comparison parts 71, 72, 73 and 74 are configured tocompare respective bit values of the counting codes Q<0:3> and the timecontrol codes IPWSET<0:3> and output a plurality of comparison resultsignals. The signal combination part 75 is configured to combine theplurality of comparison result signals outputted from the plurality ofcomparison parts 71, 72, 73 and 74, and output the period setting signalQSSETP. In other words, in an embodiment, the comparing section 1107activates and outputs the period setting signal QSSETP when the countingcodes Q<0:3> and the time control codes IPWSET<0:3> are the same witheach other.

FIG. 16 is a view illustrating configurations of the count unit shown inFIG. 9 and the second counting section shown in FIG. 13. Further, thecounter shown in FIG. 16 may be applied to the count end control partshown in FIG. 13, and may be configured using a 1-bit down counter.Hereinbelow, it will be exemplified that the counter shown in FIG. 16 isapplied to FIG. 9.

Referring to FIG. 16, the 1-bit down counter 160 may include a signalinput part 161, a latch part 163, and a borrow generation part 165.

The signal input part 161 is configured to determine the level of thesignal of an input node A of the latch part 163 according to the countenable signal DIVCNTB and the count signal DIVCNT applied to an outputnode Q.

The latch part 163 is configured to latch the signal outputted from thesignal input part 161 according to the control of the clock signalDIVCNTCK, and output the count signal DIVCNT to the output node Q.

The borrow generation part 165 is configured to output a borrow signalBOUTB, that is, the count completion signal BCNTB, according to thecount enable signal DIVCNTB and the level of the signal applied to theoutput node of the latch part 163. The borrow signal BOUTB is used as acount enable signal of a next stage 1-bit down counter. The internalnode of the latch part 163 is initialized or is changed to a specifiedlevel in response to the reset signal RSTP and the set signal DIVSETP.

In detail, the signal input part 161 selects the resultant value of theoutput node Q when the count enable signal DIVCNTB is disabled to a highlevel, and oppositely selects the resultant value of the output node Qand transfers the oppositely selected resultant value to a next stagewhen the count enable signal DIVCNTB is enabled to a low level.

The signal selected by the signal input part 161 is applied to the nodeA. Accordingly, the latch part 163 transfers the signal of the node A toa node C when the signal of the node A is a low level, and transfers thesignal of the node A to the output node Q when the signal of the node Ais a high level.

If the set signal DIVSETP becomes a high level, the output node Q is setto a high level. If the reset signal RSTP becomes a high level, theoutput node Q is reset to a low level.

The borrow generation part 165 outputs the borrow signal BOUTB of a lowlevel when the output node Q of a previous stage 1-bit down counterbecomes a low level, and transfers the borrow signal BOUTB to a nextstage 1-bit down counter. Accordingly, only when the level of the borrowsignal BOUTB by the previous stage 1-bit down counter is low, thenext-stage 1-bit down counter may toggle.

FIG. 17 is a view exemplifying a write driver which may included in thepresent invention.

Referring to FIG. 17, the write driver 400 may include a currentcontrolling section 410, a current driving section 420, and a selectingsection 430.

The current controlling section 410 is configured to receive the dataDATA to be programmed, and control the voltage level of a control nodeN1 according to a code combination of the first write control signalRESETEN and the second write control signals SETP<0:3> when the writeenable signal WDEN is activated. A plurality of NMOS transistors, whichare controlled by the second write control signals SETP<0:3>, areselectively turned on and control the voltage level of the control nodeN1. An NMOS transistor, which is controlled by the first write controlsignal RESETEN, is turned on when the first write control signal RESETENis activated and controls the voltage level of the control node N1.

The second write control signals SETP<0:3> are signals which arecyclically updated, and the first write control signal RESETEN is asignal which is inputted in the form of a pulse.

The current driving section 420 is configured to drive the programmingcurrent pulse I_PGM which has a magnitude corresponding to the voltagelevel of the control node N1. The current driving section 420 may drivethe current pulse I_PGM to an output node N2. The programming currentpulse I_PGM may be divided into a first programming current pulse whichcorresponds to the first write control signal RESETEN and a secondprogramming current pulse which corresponds to the second write controlsignals SETP<0:3>.

The selecting section 430 is configured to output the programmingcurrent pulse I_PGM driven by the current driving section 420 to bitlines BL0 to BLm corresponding to the plurality of bit line selectswitch control signals YSW<0:m>.

FIG. 18 is a timing diagram illustrating operations of a semiconductormemory apparatus according to a divisional program mode. Descriptionswill be made with additional reference back to FIG. 9.

When the number of division times is 1 (division mode 1), both thedivision option codes DIVMODE<0:1> may be low levels, and in this case,the count unit 210 does not operate and the pulse outputting section 233of the divisional program pulse generation unit 230 transfers theprogramming enable signal PGMP as the divisional programming enablesignal DIVPGMP as it is. The divisional period enable signal IDIVPGM isoutputted at a high level.

Accordingly, all the division codes DIVPGM<0:x> outputted from thedivisional code generating section 241 of the region select control unit240 become high levels. That is to say, write drivers for controlling amemory region selected without dividing the memory region are all drivenand a program operation is performed.

A reset pulse is supplied to a cell where reset data is to beprogrammed, by the first write control signal RESETEN, and a set pulseis supplied to a cell where set data is to be programmed, by the secondwrite control signals SETP<0:n>.

When the number of division times is 2 (division mode 2), the divisionoption codes DIVMODE<0:1> may respectively be a high level and a lowlevel, and the divisional programming enable signal DIVPGMP is generatedfrom the program completion signal PGMNDP which is generated after afirst program operation is completed. Moreover, the divisional codegenerating section 241 of the region select control unit 240 enables theeven-numbered division codes DIVPGM<0, 2, 4, 6> in a first divisionalprogram mode, and enables the odd-numbered division codes DIVPGM<1, 3,5, 7> in a second divisional program mode.

Similarly, when the number of division times is 4 (division mode 4), thedivisional code generating section 241 of the region select control unit240 enables the division codes DIVPGM<0, 4> in a first divisionalprogram mode, enables the division codes DIVPGM<1, 5> in a seconddivisional program mode, enables the division codes DIVPGM<2, 6> in athird divisional program mode, and enables the division codes DIVPGM<3,7> in a fourth divisional program mode.

Furthermore, when the number of division times is 8 (division mode 8),the divisional code generating section 241 of the region select controlunit 240 sequentially enables the division codes DIVPGM<0:7> andtransfers the sequentially enabled division codes DIVPGM<0:7> to thewrite driver and the controller.

Each divisional program operation is started by the divisionalprogramming enable signal DIVPGMP, the divisional programming enablesignal DIVPGMP is generated from the program completion signal PGMNDP asdescribed above.

FIG. 19 is a timing diagram illustrating program operations in the casewhere the number of division times is 4.

As the program command PGM is applied, the programming enable signalPGMP is generated from the controller 300, and the divisional programpulse generation unit 230 transfers the programming enable signal PGMPwithout modification as the divisional programming enable signalDIVPGMP.

Among the division codes outputted from the region select control unit240, the division codes DIVPGM<0, 4> are enabled in a first divisionalprogram mode as described above with reference to FIG. 18.

Meanwhile, the initial pulse generation unit 110 generates the internalclock enable signal IPWEN. After the internal clock ICK is generatedfrom the internal clock enable signal IPWEN, the counting codes Q<0:3>are generated by counting the predetermined time, and the period settingsignal QSSETP is generated when the counting is completed.

The reset pulse generation unit 120 enables the first write controlsignal RESETEN in response to the programming enable signal PGMP, and,as the reset signal IRSTP generated by delaying the period settingsignal QSSETP by the predefined time is enabled, the reset pulsegeneration unit 120 disables the first write control signal RESETEN.During the period in which the first write control signal RESETEN isenabled, the programming current is generated from the write driver 400and is provided to the bit line BL0.

The quenching pulse generation unit 130 generates the count enablesignal CKEN (CNTENB) and the internal clock QSCK in response to theperiod setting signal QSSETP. Further, according to this fact, thequenching pulse generation unit 130 generates the second write controlsignals SETP<0:3> which have different enable periods. When generationof the second write control signals SETP<0:3> is completed, thequenching pulse completion signal QSND is disabled, and, as the resetsignal QSRSTP is enabled accordingly, the program completion signalPGMNDP is outputted. In this case, as the current driving force of thewrite driver 400 is sequentially damped according to the enable periodsof the second write control signals SETP<0:3>, a quenching pulse isprovided to a memory cell. In an embodiment, the write driver 400 has acorresponding connection with a unit of bit lines where the unit of bitlines is comprised of a predetermined number of bit lines.

Since the number of division times is 4, a second program operation isperformed by the program completion signal PGMNDP. At this time, as thedivision codes DIVPGM<1, 5> are enabled, program is performed throughthe process as described above.

The division codes DIVPGM<2, 6> are enabled in a third divisionalprogram mode and the division codes DIVPGM<3, 7> are enabled in a fourthdivisional program mode, and a reset pulse and a set pulse are suppliedaccording to the first write control signal RESETEN and the second writecontrol signals SETP<0:n>, by which a program operation is implemented.

In this way, in an embodiment of the present invention, when data to beprogrammed are simultaneously inputted from a host, a region of a memoryblock to be programmed is internally divided, and the simultaneouslyinputted data are programmed by being divided.

As a consequence, since it is possible to prevent the influence of noiseresulting from peak current generation, program operations can beperformed in a stable and precise manner.

While certain embodiments have been described above, it will beunderstood to those skilled in the art that the embodiments describedare by way of example only. Accordingly, the semiconductor memoryapparatus, and the divisional program control circuit and the programmethod therefor described herein should not be limited based on thedescribed embodiments. Rather, the semiconductor memory apparatus, andthe divisional program control circuit and the program method therefordescribed herein should be understood in light of the claims that followwhen taken in conjunction with the above description and accompanyingdrawings.

What is claimed is:
 1. A semiconductor memory apparatus comprising: aprogram pulse generation block configured to generate write controlsignals and a program completion signal in response to a programmingenable signal; a divisional program control circuit configured togenerate a divisional programming enable signal according to apredetermined number of program division times and a level of adivisional period enable signal which indicates a divisional programmode, in response to the program completion signal and the divisionalperiod enable signal; and a controller configured to generate theprogramming enable signal in response to the divisional programmingenable signal.
 2. The semiconductor memory apparatus according to claim1, wherein the program pulse generation block generates the writecontrol signals in response to the programming enable signal, andgenerates the program completion signal when an operation for generatingthe write control signals is completed.
 3. The semiconductor memoryapparatus according to claim 1, wherein the divisional program controlcircuit generates the divisional programming enable signal through acounting operation according to the predetermined number of programdivision times where the divisional programming enable is generated inresponse to the program completion signal.
 4. The semiconductor memoryapparatus according to claim 3, wherein the divisional program controlcircuit generates division codes in response to division mode signalswhich designate divisional program regions in correspondence to thepredetermined number of program division times.
 5. The semiconductormemory apparatus according to claim 4, further comprising: a writedriver configured to be driven according to the division codes andprovide program current generated in response to the write controlsignals to a memory block.
 6. The semiconductor memory apparatusaccording to claim 1, further comprising: a write driver configured togenerate program current corresponding to the write control signals andprogram data to a memory block.
 7. The semiconductor memory apparatusaccording to claim 6, wherein the program pulse generation blockgenerates the write control signals a number of times corresponding tothe predetermined number of program division times, and the write driveris connected with a unit of bit lines comprising a predetermined numberof bit lines, and wherein the controller drives a corresponding writedriver when the write control signals are generated, and programs datato the memory block.
 8. The semiconductor memory apparatus according toclaim 6, wherein the memory block includes a plurality of memory cellsin and from which data are recorded and sensed in a current drivingscheme.
 9. A semiconductor memory apparatus comprising: a program pulsegeneration block configured to output write control signals in responseto a programming enable signal which is generated according to adivisional programming enable signal; and a write driver configured toprovide a program pulse generated in response to the write controlsignals, to a memory block, wherein the divisional programming enablesignal is generated in response to a program completion signal and thedivisional period enable signal which indicates a divisional programmode.
 10. The semiconductor memory apparatus according to claim 9,wherein the divisional programming enable signal is enabled incorrespondence to a predetermined number of program division times. 11.The semiconductor memory apparatus according to claim 10, wherein theprogram pulse generation block generates the write control signals anumber of times corresponding to the predetermined number of programdivision times.
 12. The semiconductor memory apparatus according toclaim 9, wherein the program pulse generation block generates a programcompletion signal after the write control signals are generated, andgenerates the divisional programming enable signal in response to theprogram completion signal.
 13. The semiconductor memory apparatusaccording to claim 9, wherein the write control signals include a firstwrite control signal for programming data of a first level and secondwrite control signals for programming data of a second level.
 14. Adivisional program control circuit, wherein the divisional programcontrol circuit is connected with a program pulse generation block whichgenerates a program completion signal, in response to a programmingenable signal which is generated according to a divisional programmingenable signal, and wherein the divisional program control circuitgenerates the divisional programming enable signal according to apredetermined number of program division times, in response to theprogram completion signal, wherein the divisional programming enablesignal is generated in response to a program completion signal and thedivisional period enable signal which indicates a divisional programmode.
 15. The divisional program control circuit according to claim 14,wherein the divisional program control circuit comprises: a count unitconfigured to generate count signals and count completion signalsthrough a counting operation responsive to the program completionsignal; a mode determination unit configured to generate a modedetermination signal in response to the count completion signals anddivision mode signals which designate divisional program regions; adivisional program pulse generation unit configured to be drivenaccording to the mode determination signal and generate the divisionalprogramming enable signal in response to the programming enable signaland the program completion signal; and a region select control unitconfigured to be driven according to the mode determination signal andoutput division codes in response to the division mode signals and thecount signals.
 16. The divisional program control circuit according toclaim 15, wherein the divisional program pulse generation unit outputsany one of the programming enable signal and the program completionsignal as the divisional programming enable signal.
 17. The divisionalprogram control circuit according to claim 15, wherein the count unitcomprises a plurality of counters which are connected in series to counta number of divisional program times in response to a count enablesignal, a clock signal generated from the program completion signal, aset signal and a reset signal.
 18. The divisional program controlcircuit according to claim 17, wherein each counter comprises a downcounter.
 19. The divisional program control circuit according to claim15, wherein the divisional program pulse generation unit comprises: aperiod setting section configured to generate divisional period enablesignal, where the divisional period enable signal is generated inresponse to the mode determination signal, the clock signal, the setsignal and the reset signal; and a pulse outputting section configuredto output the divisional programming enable signal in response to thedivisional period enable signal, the programming enable signal and theprogram completion signal.
 20. The divisional program control circuitaccording to claim 19, wherein the period setting section comprises adown counter.
 21. The divisional program control circuit according toclaim 19, wherein the region select control unit comprises a divisionalcode generating section configured to be driven according to the modedetermination signal and generate the division codes in response to thedivisional period enable signal, the division mode signals and the countsignals.
 22. The divisional program control circuit according to claim21, wherein the division mode signals are preset to a fuse option, amode register set or a test mode signal.
 23. The divisional programcontrol circuit according to claim 21, wherein the division programcontrol circuit drives a write driver by the division codes.
 24. Aprogram method for a semiconductor memory apparatus, comprising:inputting program data to the semiconductor memory apparatus comprisinga program pulse generation block; repeatedly generating a programmingenable signal with a preset cycle in correspondence to a predeterminednumber of program division times by the program pulse generation block,in response to a program completion signal and a divisional periodenable signal which indicates a divisional program mode; and programmingdata to a selected region of a memory block by a write driver, inresponse to the programming enable signal.
 25. The method according toclaim 24, wherein the data is programmed to the selected region of thememory block according to write control signals which are generated inresponse to the programming enable signal, and wherein the methodfurther comprises: outputting program completion signal after the writecontrol signals are generated.
 26. The method according to claim 25,wherein the programming enable signal is repeatedly generated with agenerating cycle of the program completion signal.
 27. The methodaccording to claim 25, wherein the programming enable signal isgenerated according to a divisional programming enable signal which isgenerated in response to the program completion signal.
 28. The methodaccording to claim 24, wherein the method further comprises: generatingdivision mode signals which designate divisional program regions, incorrespondence to the predetermined number of program division times,and wherein the programming of data comprises: programming data to aregion selected by the division mode signals.